The discussion of any work, publications, sales, or activity anywhere in this submission, including in any documents submitted with or during examination of this application, shall not be taken as an admission by the inventors that any such work constitutes prior art. The discussion of any activity, work, or publication herein is not an admission that such activity, work, or publication was known in any particular jurisdiction.
The great majority of electronic devices in use today employ solid-state transistors as a chief building block. Dynamic random access memories (DRAM), in particular, play an increasingly important part in determining the performance of microelectronic products. Their role has raised the demand for reliable, high density memories with fast data access and low power consumption.
A typical and very well known DRAM design employs one transistor and one storage capacitor (1T/1C) per memory cell (or bit storage location) as well as other components to provide reference cells, sense amplification, refresh, redundancy, etc. However, the basic 1T/1C memory cell design has difficulties when shrunk, particularly below about 100 nm×100 nm cell size. Reducing the transistor's off-state leakage, for example, can require high substrate doping to sustain a large threshold voltage. Unfortunately, this approach often enhances trap-assisted tunneling and can lead to tail bits with small retention times. Another difficulty is fabrication of the small storage capacitor used in traditional DRAM designs.
There is substantial interest in developing the next generation DRAM. In some proposals for capacitorless DRAM going back as far as 1993, the conventional storage capacitor is replaced by the body capacitance of a SOI MOSFET (Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistor). In some of these proposals, the number of majority carriers stored in the body can affect channel conductivity. It has been proposed that this change in channel conductivity can be used to distinguish two states in a memory device. However, previous capacitorless cell designs may be impractical for manufacturing because of their doping profiles. (See, for example, H.-J. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate”, IEDM, 1993, pp. 635-8.) Other publications have discussed partially depleted SOI (PD-SOI) MOSFET as a possible successor to conventional 1T/1C DRAMs. In October 2001, Okhonin et al. reported experimental measurements using a PD-SOI MOSFET as a capacitorless DRAM cell. In February 2002, Ohsawa et al. presented the results of a working 512 kb DRAM array with capacitorless PD-SOI cells. However, PD-SOI-based capacitorless DRAMs are also generally less practical in sub-100 nm technologies because the heavy doping levels required to sustain an undepleted body incur dopant fluctuations across many cells in an array that can result in significant threshold voltage (Vt) variations for high density memory arrays.
Furthermore, as the device is scaled, capacitorless DRAM technologies using a partially-depleted film generally require increasingly larger amounts of body doping. Heavy doping limits depletion into the body from the gate, drain, and source for sub-100 nm devices. This presents additional challenges since a large body doping can result in trap-assisted tunneling and Vt fluctuations. While dopant fluctuations may be tolerable for wider logic devices, substantial variations in threshold voltage are generally significant for high density arrays using small-geometry cells. This can be especially true for capacitorless DRAM arrays in which the difference in threshold voltages between two states can be only a few hundred millivolts.
U.S. Pat. No. 6,088,260 discusses a capacitorless memory with a relatively thicker silicon body to accommodate a source/drain junction that is not contacted with the buried oxide layer and wherein a purging region is needed to serve as a body contact, which may limit the ability to achieve very small cell sizes. The body in this structure is not truly floating as there is a contact to the body through the purge region.